1. Technical Field
The present invention relates to an active matrix type display device in which a current-driven emissive element is provided in each of pixels arranged in a matrix and the current of the emissive element is controlled using a drive TFT to perform display.
2. Related Art
FIG. 1 shows a configuration of a circuit for one pixel (pixel circuit) in a basic active type organic EL display device. A gate line (Gate) extending in the horizontal direction is set to HIGH level so as to turn on a selection TFT 1. In this state, an image data signal (also referred to as “data voltage”) having a voltage in accordance with a display brightness is supplied to a data line (Data) extending in the vertical direction. The image data signal is thereby accumulated in a storage capacitor C provided between the gate and source of a drive TFT 2. As a result of this, the drive TFT (in this example, P-type TFT) 2 having the source connected to a power supply PVdd supplies a drive current in accordance with the data signal to an organic EL element 3 connected to the drain of the drive TFT 2. Accordingly, the organic EL element 3 emits light in accordance with the data signal.
FIG. 2 shows an example configuration of a display panel and input signals. In FIG. 2, the image data signal, horizontal synchronization signal (HD), pixel clock, and other drive signals are supplied to a source driver 4. The image data signal is transmitted in synchronization with the pixel clock to the source driver 4. In the source driver 4, when the image data signal for pixels of one horizontal line is taken in, that image data signal is retained in a latch circuit provided therein, collectively subjected to D-A conversion, and then supplied to the data lines of the corresponding columns. Further, the horizontal synchronization signal (HD), other drive signals, and vertical synchronization signal (VD) are supplied to a gate driver 5. The gate driver 5 sequentially turns on the gate lines (Gate) provided along each row extending in the horizontal direction, to perform control such that the image data signal is supplied to the pixels in the corresponding rows. Each of the pixels 6 arranged in the matrix includes the pixel circuit shown in FIG. 1.
Using an arrangement as described above, the image data signal (data voltage) is sequentially written into the respective pixels in units of a horizontal line, and a display in accordance with the written image data signal is performed in each pixel, thereby, as an overall panel, achieving a screen display.
Here, the amount of light emission and the current of the organic EL element 3 have a substantially proportional relationship. Typically, between the gate of the drive TFT 2 and PVdd, a voltage (Vth) that causes a drain current to start to flow near the image black level is applied. Further, the amplitude of the image signal is set to an amplitude that attains a predetermined brightness near the white level.
FIG. 3 shows the relationship of current CV (corresponding to brightness) that flows through the organic EL element with respect to the signal voltage input to the drive TFT (the voltage of the data line Data). By setting the data signal such that Vb is applied as the black level voltage and Vw is applied as the white level voltage, suitable gradation control can be performed in the organic EL element.
In an active matrix type organic EL display device, there exists the problem of image lag being generated due to a hysteresis characteristic of the drive TFT. This problem can be clearly perceived particularly in a case in which first a white window is displayed on a gray background and then the entire screen is switched to display a gray image. In this case, as shown in FIG. 4, the portion in which the white window was displayed until just a moment before becomes slightly darker than other portions, and it may take several seconds to several tens of seconds until the brightness level becomes the same as the other portions. This problem is caused by the phenomenon that, even when the drive TFT of a certain pixel is driven by the same data voltage, the drive current value varies depending on the current that was made to flow several seconds before. It is considered that this phenomenon occurs because the carriers (holes) that flow through the drive TFT become trapped within the gate insulation film, thereby changing the Vth of the drive TFT. In terms of visual perception, this problem is most noticeable when a change is made from a high brightness to a brightness of an intermediate tone. On the other hand, when a change is made from a low brightness to an intermediate-tone brightness or to a high brightness, the problem is not very noticeable. The degree of image lag also depends on the duration of image display in the immediately preceding period. The image lag becomes more noticeable when this duration is longer.
It has been known that the carriers (holes) within the gate insulation film can be eliminated by applying between the gate and source of the drive TFT an opposite bias voltage, i.e., a voltage higher than the PVdd connected to the source. The effect of the opposite bias voltage becomes greater when the opposite bias voltage is higher and is applied for a longer duration. This opposite bias voltage is often applied in each frame for a plurality of line periods before the pixel data are updated.
For example, as shown in FIG. 5, a transistor 7 is added to the pixel circuit. The transistor 7 is of n-channel type, and has a gate connected to a control line CTL, a drain connected to an opposite biasing power supply Va, and a source connected to the gate of the drive TFT 2. In this pixel circuit, by periodically setting the CTL line to HIGH level, Va having a voltage higher than the PVdd voltage can be applied to the gate of the drive TFT 2.
As shown in FIG. 6, a CTL signal supplied to the CTL line is generated in a lights-off control circuit 8, and is sequentially set to ON (“Hi”) line by line, similarly to the Gate signal. FIG. 7 shows the timing of writing data for line m and line m+1. Until t1, in pixel (m, n) located in the mth row and nth column, the pixel data that was written during the previous frame is retained in the storage capacitor C, and a pixel current in accordance with that voltage flows in the pixel. When Va is written in the storage capacitor C during t1-t2, the opposite bias voltage is applied between the gate and source of the drive TFT 2, such that the drain current becomes zero. During t3-t4, new pixel data is written in, and a pixel current flows again.